DESIGN OF A FULL ADDER CIRCUIT

ABSTRACT

In this project, two high performance adder cells are proposed. We simulated these two full adder cells using HSPICE in 0.18 µm, CMOS technology and at 25-degree of temperature with supply voltage range from 0.5v to 3.3v with 0.1v steps. Results show that the proposed adders operate successfully when connected to a 0.5 V power supply. The two adders differ in the technology applied to their gates. While the first circuit applies CMOS technology, the second and optimal one uses Past Transistor Logic. The average power dissipation of the optimum is 4.3269*10-7 watt, which illustrates an amazing performance. This paper demonstrates the PDP and Power Consumption of the proposed adders, and the comparison results among another six full adders.

CHAPTER ONE

1.0 INTRODUCTION

Adder is one of the most important components of a CPU (central processing unit). Arithmetic logic unit (ALU), floating-point unit and address generation like cache or memory access unit use it. In addition, Full adders are important components in other applications such as digital signal processors (DSP) architectures and microprocessors [1-5]. Arithmetic functions such as ‘addition’, ‘subtraction’, ‘multiplication’ and ‘division’ are some examples, which use ‘adder’ as a main building block. As a result, design of a high-performance full-adder is very useful and important [2, 3, 6-8]. On the other hand, increasing demand for portable equipments such as cellular phones, personal digital assistant (PDA), and notebook personal computer, arises the need of using area and power efficient VLSI circuits[2, 9-12]. Low-power and high-speed adder cells are used in battery-operation based devices [13-15].

1.1   Half adder

The half adder is an example of a simple, functional digital circuit built from two logic gates. A half adder adds two one-bit binary numbers A and B. It has two outputs, S and C (the value theoretically carried on to the next addition); the final sum is 2C + S. The simplest half-adder design, pictured on the right, incorporates an XOR gate for S and an AND gate for C. Half adders cannot be used compositely, given their incapacity for a carry-in bit.